Cache memory designs support either or both of two basic write policies: write-through or write-back. In write-through mode, each write to a cache line also results in an external bus cycle to write the corresponding block of main memory--as a result, the cache and main memory always have the same data. In write-back mode, writes to the cache do not automatically cause an external bus-write cycle, but rather, main memory is updated only upon replacement, invalidation, or inquiry (write-back without replacement or invalidation) of a cache line containing "dirty" data--data is characterized as "clean" or "dirty" depending on whether the data in the cache is different from the main memory.
In a multi-master computer system, main memory may be accessed by bus masters other than the CPU, including DMA devices and microcontrollers (as well as other CPUs). To maintain coherency between cache memory and main memory, the CPU typically will implement one of two cache coherency techniques: (a) bus snooping--monitoring all addressing operations to detect when another bus master has accessed cached memory locations, or (b) bus arbitration--detecting when another bus master requires control of the system bus such that it may access cacheable regions in main memory. In the case of bus arbitration, the CPU and the other bus masters commonly use bus arbitration signals--such as HOLD and HLDA (HOLD Acknowledge)--as a request-acknowledge handshake protocol for arbitrating control of the memory bus (i.e., any bus that can access memory) and thereby access main memory. To ensure cache coherency, the CPU should invalidate at least those cache locations containing addresses that are accessed by another bus master (the actual cache coherency policy will depend upon a number of factors such as write-through/write-back and whether the CPU is able to snoop the bus to detect addresses driven by the external bus master).
Without limiting the scope of the invention, this background information is provided in the context of a specific problem to which the invention has application: providing a 486-type microprocessor that implements write-back caching along with a cache coherency mechanism to permit installation in a conventional 486-based computer system designed for write-through cache, i.e., either without support for a write-back protocol, or with only limited support for write back caching.
The current 486 generation microprocessor from Intel Corporation only supports write-through caching for its internal cache, even though, as described in the related application (1), the microprocessor includes a control bit for selecting between write-through and write-back caching. Providing a 486-type microprocessor with write-back cache support could provide significant performance advantages because of the reduction in memory bandwidth requirements--fewer external bus cycles are required because not all writes to the cache result in corresponding writes to main memory, and such performance enhancing techniques as write gathering and burst writes become possible.
A 486-based computer system could be configured to support write-back caching, and in particular, to provide the necessary support for a write-back protocol (including snooping and support for any additional microprocessor pins used to implement write-back caching while ensuring cache coherency). However, any new microprocessor design would preferably support installation in any 486-based computer system, whether or not it supported write-back caching and an associated write-back protocol.
Use of such a 486-type microprocessor in a multi-master computer system that lacks support for a write-back protocol presents problems in maintaining cache coherency. The related application (2) discloses a mechanism for maintaining cache coherency for a microprocessor with internal cache designed for installation in conventional 386-based computer systems--the conventional 386-generation microprocessor does not include internal cache, and these systems sometimes do not provide the normal HOLD/HLDA bus master arbitration signals to the microprocessor (or do not otherwise provide for cache coherency such as with bus snooping). However, 486-based computer systems, which are designed for a microprocessor with internal cache, present different cache coherency issues in attempting to introduce write-back caching: (a) data integrity, and (b) compatibility with cache invalidation specifications.
Data integrity is implicated because of the bus arbitration protocol used to grant memory access to bus masters--an external bus master (such as a disk controller) requests control of the bus by asserting HOLD, and then, after HLDA is returned by the microprocessor, asserts FADS while driving addresses onto the memory bus. This is not a problem for write-through cache designs because main memory contains the most current copy of data--when the bus is arbitrated away using the HOLD/HLDA protocol, the microprocessor snoops the bus and invalidates any cache lines containing addresses driven by the external bus master. However, for a write-back cache design, the most current copy of data may be in the cache rather than in main memory--if the bus master attempts to access memory locations for which corresponding locations in the cache contain dirty data, coherency will be violated without a write-back coherency protocol (a) to allow the microprocessor to monitor each address driven by the bus master, and (b) for addresses representing dirty data, to write back or flush (write-back and invalidate) the associated cache line (or, at least, the dirty data).
Compatibility with cache invalidation specifications is implicated because the conventional 486-type microprocessor specification requires single-cycle cache line invalidation--when a bus master drives an address after asserting EADS, the microprocessor is expected to invalidate the corresponding cache line (in the case of a cache hit) in a single dock cycle. A flush operation involving both write-back and invalidation would typically require two clock cycles to complete.
Moreover, while the 486-instruction set includes INVD and WBINVD cache invalidation instructions that differentiate between write-through and write-back cache, the WBINVD instruction is only supported for external write-back cache (because the conventional 486-type microprocessor only supports a write-through internal cache). Thus, software written for conventional 486-type microprocessor may use the INVD instruction for the internal write-through cache, which would cause a coherency problem if the internal cache were write-back.
Another compatibility issue is presented by LOCK operations. In the 486-instruction set, a microprocessor executing a LOCKed bus cycle is given control of the memory bus for a read-modify-write operation (such as for semaphore operations). The conventional approach is to send the read and the write to the bus to access external memory, regardless of whether the data is in the cache--many computer system chipsets expect to see both the read and the write for a LOCKed bus cycle. However, in a write back environment, the external memory may not have the most current copy of data.
Accordingly, a specific object of the invention is to provide a design for a 486-type microprocessor that supports write-back cache, including implementing a cache coherency mechanism to support installation in a computer system that at most supports limited write-back protocol for maintaining cache coherency, and provides support for LOCKed bus cycles in a manner compatible with existing computer systems.